Hardware apparatuses and methods for memory corruption detection

ABSTRACT

Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a continuation application claiming priorityfrom U.S. patent application Ser. No. 17/020,663 filed Sep. 14, 2020,now U.S. Pat. No. 11,645,135, which is a continuation applicationclaiming priority from U.S. patent application Ser. No. 16/224,579 filedDec. 18, 2018, now U.S. Pat. No. 10,776,190, which is a continuationapplication claiming priority from U.S. patent application Ser. No.14/977,354 filed Dec. 21, 2015, now U.S. Pat. No. 10,162,694, each ofwhich is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The disclosure relates generally to electronics, and, more specifically,an embodiment of the disclosure relates to a hardware processor withmemory corruption detection hardware.

BACKGROUND

A processor, or set of processors, executes instructions from aninstruction set, e.g., the instruction set architecture (ISA). Theinstruction set is the part of the computer architecture related toprogramming, and generally includes the native data types, instructions,register architecture, addressing modes, memory architecture, interruptand exception handling, and external input and output (I/O). It shouldbe noted that the term instruction herein may refer to amacro-instruction, e.g., an instruction that is provided to theprocessor for execution, or to a micro-instruction, e.g., an instructionthat results from a processor's decoder decoding macro-instructions.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is illustrated by way of example and notlimitation in the figures of the accompanying drawings, in which likereferences indicate similar elements and in which:

FIG. 1 illustrates a hardware processor according to embodiments of thedisclosure.

FIG. 2 illustrates memory corruption detection (MCD) according toembodiments of the disclosure.

FIG. 3 illustrates a pointer format with an address field and without amemory corruption detection (MCD) value field according to embodimentsof the disclosure.

FIG. 4 illustrates a pointer format with an address field and a memorycorruption detection (MCD) value field according to embodiments of thedisclosure.

FIG. 5 illustrates a pointer format with an address field, a memorycorruption detection (MCD) space field, and a memory corruptiondetection (MCD) value field according to embodiments of the disclosure.

FIG. 6 illustrates data formats of registers for memory corruptiondetection (MCD) according to embodiments of the disclosure.

FIG. 7 illustrates a memory corruption detection (MCD) system with amemory management unit according to embodiments of the disclosure.

FIG. 8 illustrates a memory management unit according to embodiments ofthe disclosure.

FIG. 9 illustrates a pointer format with an address field and without amemory corruption detection (MCD) value field according to embodimentsof the disclosure.

FIG. 10 illustrates a pointer format with an address field and without amemory corruption detection (MCD) value field according to embodimentsof the disclosure.

FIG. 11 illustrates a pointer format with an address field, a memorycorruption detection (MCD) space field, and a memory corruptiondetection (MCD) value field according to embodiments of the disclosure.

FIG. 12A illustrates a linear address space according to embodiments ofthe disclosure.

FIG. 12B illustrates a view of a portion of the linear address space inFIG. 12A according to embodiments of the disclosure.

FIG. 12C illustrates a view of the portion of the linear address spacein FIG. 12B with a subset of memory corruption detection (MCD) protectedspace according to embodiments of the disclosure.

FIG. 13 illustrates a pointer format with an address field and without amemory corruption detection (MCD) value field according to embodimentsof the disclosure.

FIG. 14 illustrates a pointer format with an address field, a memorycorruption detection (MCD) space field, and a memory corruptiondetection (MCD) value field according to embodiments of the disclosure.

FIG. 15A illustrates a linear address space according to embodiments ofthe disclosure.

FIG. 15B illustrates a view of a portion of the linear address space inFIG. 15A according to embodiments of the disclosure.

FIG. 15C illustrates a view of the portion of the linear address spacein FIG. 12B with a subset of memory corruption detection (MCD) protectedspace according to embodiments of the disclosure.

FIG. 16 illustrates a pointer format with an address field, a memorycorruption detection (MCD) space field, and a memory corruptiondetection (MCD) value field according to embodiments of the disclosure.

FIG. 17A illustrates a linear address space according to embodiments ofthe disclosure.

FIG. 17B illustrates a view of a portion of the linear address space inFIG. 17A according to embodiments of the disclosure.

FIG. 17C illustrates a view of the portion of the linear address spacein FIG. 17B with a subset of memory corruption detection (MCD) protectedspace according to embodiments of the disclosure.

FIG. 18 illustrates a flow diagram according to embodiments of thedisclosure.

FIG. 19A is a block diagram illustrating both an exemplary in-orderpipeline and an exemplary register renaming, out-of-orderissue/execution pipeline according to embodiments of the disclosure.

FIG. 19B is a block diagram illustrating both an exemplary embodiment ofan in-order architecture core and an exemplary register renaming,out-of-order issue/execution architecture core to be included in aprocessor according to embodiments of the disclosure.

FIG. 20A is a block diagram of a single processor core, along with itsconnection to the on-die interconnect network and with its local subsetof the Level 2 (L2) cache, according to embodiments of the disclosure.

FIG. 20B is an expanded view of part of the processor core in FIG. 20Aaccording to embodiments of the disclosure.

FIG. 21 is a block diagram of a processor that may have more than onecore, may have an integrated memory controller, and may have integratedgraphics according to embodiments of the disclosure.

FIG. 22 is a block diagram of a system in accordance with one embodimentof the present disclosure.

FIG. 23 is a block diagram of a more specific exemplary system inaccordance with an embodiment of the present disclosure.

FIG. 24 is a block diagram of a second more specific exemplary system inaccordance with an embodiment of the present disclosure.

FIG. 25 is a block diagram of a system on a chip (SoC) in accordancewith an embodiment of the present disclosure.

FIG. 26 is a block diagram contrasting the use of a software instructionconverter to convert binary instructions in a source instruction set tobinary instructions in a target instruction set according to embodimentsof the disclosure.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth.However, it is understood that embodiments of the disclosure may bepracticed without these specific details. In other instances, well-knowncircuits, structures and techniques have not been shown in detail inorder not to obscure the understanding of this description.

References in the specification to “one embodiment,” “an embodiment,”“an example embodiment,” etc., indicate that the embodiment describedmay include a particular feature, structure, or characteristic, butevery embodiment may not necessarily include the particular feature,structure, or characteristic. Moreover, such phrases are not necessarilyreferring to the same embodiment. Further, when a particular feature,structure, or characteristic is described in connection with anembodiment, it is submitted that it is within the knowledge of oneskilled in the art to affect such feature, structure, or characteristicin connection with other embodiments whether or not explicitlydescribed.

A (e.g., hardware) processor (e.g., having one or more cores) mayexecute instructions to operate on data, for example, to performarithmetic, logic, or other functions. A hardware processor may accessdata in a memory (e.g., a data storage device). In one embodiment, ahardware processor is a client requesting access to (e.g., load orstore) data and the memory is a server containing the data. In oneembodiment, a computer includes a hardware processor requesting accessto (e.g., load or store) data and the memory is local to the computer.Memory may be divided into separate lines (e.g., one or more cachelines) of data, for example, that may be managed as a unit for coherencepurposes. In certain embodiments, a (e.g., data) pointer (e.g., anaddress) is a value that refers to (e.g., points) the location of data,for example, a pointer may be an (e.g., linear) address and the data maybe stored at that (e.g., linear) address. In certain embodiments, memorymay be divided into multiple lines and each line may have its own (e.g.,unique) address. For example, a line of memory may include storage for512 bits, 256 bits, 128 bits, 64 bits, 32 bits, 16 bits, or 8 bits ofdata.

In certain embodiments, memory corruption (e.g., by an attacker) may becaused by an out-of-bound access (e.g., memory access using the baseaddress of a block of memory and an offset that exceeds the allocatedsize of the block) or by a dangling pointer (e.g., a pointer whichreferenced a block of memory (e.g., buffer) that has been de-allocated).

Certain embodiments herein may utilize memory corruption detection (MCD)hardware and/or methods, for example, to prevent an out-of-bound accessor an access with a dangling pointer.

Turning now to the figures, FIG. 1 illustrates a hardware processor 100according to embodiments of the disclosure. Depicted hardware processor100 includes a hardware decode unit 102 to decode an instruction, e.g.,an instruction that is to request access to a block of a memory 110through a pointer 105 to the block of the memory 110. Pointer 105 may bean operand of the instruction. Depicted hardware execution unit 104 isto execute the decoded instruction, e.g., the decoded instruction thatis to request access to the block of the memory 110 through a pointer105 (e.g., having a value of the (e.g., linear) address 114) to theblock of the memory 110. In one embodiment, a block of data is a singleline of data. In one embodiment, a block of data is multiple lines ofdata. For example, a block of memory may be lines 1 and 2 of data of the(e.g., linear or physical) addressable memory 112 of memory 110 thatincludes a pointer 105 (e.g., having a value of the address 114) to one(e.g., the first) line (e.g., line 1). Certain embodiments may have amemory of a total size of X number of lines.

Hardware processor 100 may include one or more register 108, forexample, control register or configuration registers, such as, but notlimited to, model specific register (MSR) or other registers. In oneembodiment, a value stored in a control register is to change (e.g.,control) selectable features, for example, features of the hardwareprocessor.

Hardware processor 100 includes a coupling (e.g., connection) to amemory 110. Memory 110 may be a memory local to the hardware processor(e.g., system memory). Memory 110 may be a memory separate from thehardware processor, for example, memory of a server. Note that thefigures herein may not depict all data communication connections. One ofordinary skill in the art will appreciate that this is to not obscurecertain details in the figures. Note that a double headed arrow in thefigures may not require two-way communication, for example, it mayindicate one-way communication (e.g., to or from that component ordevice). Any or all combinations of communications paths may be utilizedin certain embodiments herein.

Hardware processor 100 includes a memory management unit 106, forexample, to perform and/or control access (e.g., by the execution unit104) to the (e.g., addressable memory 112 of) memory 110. In oneembodiment, hardware processor includes a connection to the memory.Additionally or alternatively, memory management unit 106 may include aconnection to the (e.g., addressable memory 112 and/or memory corruptiondetection table 116 of) memory 110.

Certain embodiments may include memory corruption detection (MCD)features, for example, in a memory management unit. Certain embodimentsmay utilize a memory corruption detection (MCD) value in each pointerand a corresponding (e.g., matching) MCD value saved in the memory forthe memory being pointed to, for example, saved as metadata (e.g., datathat describes other data) for each block of data being pointed to bythe pointer. A MCD value may be a sequence of bits, for example, a 2, 3,4, 5, 6, 7, 8. 9, 10, 11, 12, 13, 14, 15, 16 bits, etc. In oneembodiment, a memory corruption detection (MCD) hardware processingsystem or processor (e.g., a memory management unit of the processor orsystem) is to validate pointers produced by instructions of theapplications being executed by the processing system or processor thatrequest access to the memory.

Certain embodiments herein (e.g., of settings of an MMU circuit) utilizeone of more of the following attributes for memory corruption detection:MCD enabled (e.g., to turn the MCD feature on or off), MCD position(e.g., to define the bit position(s) of MCD values (metadata) inpointers), MCD protected space, for example, a prefix in the mostsignificant bit positions of the pointer (e.g., to define the linearaddress range that is to be protected by the architecture), and MCDdirectory base (e.g., to point to the memory MCD value (e.g., metadata)table (e.g., directory)).

Certain embodiments herein allow the flexible placement of MCD values(e.g., metadata bits) into a pointer, e.g., not limited to the mostsignificant bits. Certain embodiments herein allow for carving out asmaller address space (e.g., reduction in linear address space overhead)and/or for scaling for (e.g., 64 bit) paging modes. Certain embodimentsherein allow protection with MCD for only a subset (e.g., part of)memory through a protected space selection (e.g., selecting theaddress(es) to protect with MCD and not protecting the other addresseswith MCD).

In FIG. 1 , memory management unit 106 (e.g., hardware memory managementunit) of hardware processor 100 may receive a request to access (e.g.,load or store) memory 110 (e.g., addressable memory 112). The requestmay include a pointer 105 (e.g., having a value of address 114), forexample, passed in as an operand (e.g., direct or indirect) of aninstruction. Pointer may include as a portion (e.g., field) thereof amemory corruption detection (MCD) value. A multiple line block of memorymay include an MCD value for that block, e.g., a same MCD value for allof the lines in that block, and the MCD value for that block is tocorrespond to (e.g., match) the MCD value inside the pointer to thatblock. Memory management unit 106 (e.g., a circuit thereof) may performan MCD validation check (e.g., to allow or deny access) according tothis disclosure.

FIG. 2 illustrates memory corruption detection (MCD) according toembodiments of the disclosure. A processing system or processor maymaintain a metadata table (e.g., MCD table 116 or MCD table 216) thatstores an MCD value (e.g., MCD identifier) for each line of a pluralityof lines of a memory block, for example, lines of a pre-defined size(e.g., 64 bytes, although other line sizes may be utilized). In oneembodiment, when a block of memory is allocated to a (e.g., newlycreated) memory object, a unique MCD value is generated and associatedwith the one or more lines of that block. The MCD value may be stored inone or more (e.g., metadata) table entries that correspond to the memoryblock being allocated for the (e.g., newly created) memory object. InFIG. 2 , data lines 1 and 2 are depicted as allocated to object 1 (e.g.,as a block of data) and an MCD value (shown here as “2”) is associatedin MCD table 216, for example, such that each data line is associatedwith an entry in the MCD table 216 that indicates the MCD value (e.g.,“2”) for that block. In FIG. 2 , data lines 3-5 are depicted asallocated to object 2 (e.g., as a block of data) and an MCD value (shownhere as “7”) is associated in MCD table 216, for example, such that eachdata line is associated with an entry in the MCD table 216 thatindicates the MCD value (e.g., “7”) for that block. In one embodiment,the MCD table 216 has an MCD value field for each corresponding line ofthe addressable memory 112.

In certain embodiments, the generated MCD value, or a different valuethat corresponds or maps to the generated MCD value for the block ofdata, is stored in one or more bits of a pointer, e.g., a pointer thatis returned by the memory allocation routine to the application thatrequested the memory allocation. In FIG. 2 , pointer 215 includes an MCDvalue field 215A with the MCD value (“2”) and address field 215B with avalue for the (e.g., linear) address of (e.g., the first line of) theobject 1 block of memory. In FIG. 2 , pointer 217 includes an MCD valuefield 217A with the MCD value (“7”) and address field 217B with a valuefor the (e.g., linear) address of (e.g., the first line of) the object 2block of memory.

In certain embodiments, responsive to receiving a memory accessinstruction (e.g., as determined from an opcode of the instruction or anattempt to access memory), the processing system or processor comparesthe MCD value retrieved from the MCD table (e.g., for the block of datato be accessed) to the MCD value from (e.g., extracted from) the pointerspecified by the memory access instruction. In one embodiment, when thetwo MCD values match, the access to the block of data is granted. In oneembodiment, when the two MCD values mismatch, access to the block ofdata is denied, e.g., a page fault may be generated. In one embodiment,the MCD table (e.g., MCD table 116 or MCD table 216) is in the linearaddress space of the memory. In one embodiment, the circuit and/or logicto perform the MCD validation check (e.g., in memory management unit(MMU) 106) is to access the memory but the other portions of theprocessor (e.g., the execution unit) are to not access the memory unlessthe MCD validation check passes (e.g., a match is true). In oneembodiment, a request for access to a block of memory is a loadinstruction. In one embodiment, a request for access to a block ofmemory is a store instruction.

In FIG. 2 , a request to access the object 1 block in addressable memory212 of memory 210 may initiate (e.g., by a memory management unit)reading the pointer 215 for the MCD value (“2”) in MCD value field 215Aand the (e.g., linear) address in address field 215B. The system (e.g.,processor) may then perform a validation check, for example, by loadingthe MCD value from the MCD table 216 in memory 210 for the line or linesto be accessed and comparing that to the MCD value in the pointer 215 tothose line or lines. In certain embodiments, if the system determinesthat the MCD values match (e.g., both being “2” in this example), thenthe system allows (e.g., read and/or write) access to the memory (e.g.,only data lines 1 or 1 and 2). In certain embodiments, if there is nomatch, the request is denied (e.g., the requesting instruction mayfault). In one embodiment, the request to access the object 1 block mayinclude a request to access all lines in the object (data lines 1 and2), and the system may perform a validation check on data line 1 (e.g.,as discussed above) and may perform a second validation check on dataline 2. For example, the system (e.g., processor) may perform avalidation check on line 2 by loading the MCD value from the MCD table216 in memory 210 for line 2 (e.g., MCD value “2”) and comparing that tothe MCD value in the pointer 215. In certain embodiments, if the systemdetermines that the MCD values match (e.g., both MCD values being “2” inthis example), then the system allows (e.g., read and/or write) accessto the memory (e.g., data line 2).

FIG. 3 illustrates a pointer format 300 with an address field 301 andwithout a memory corruption detection (MCD) value field according toembodiments of the disclosure. In one embodiment, an address field 301contains a linear address of the data line storing the data to beaccessed. The illustrated bit positions are examples. The pointer sizeof 64 bits is an example.

FIG. 4 illustrates a pointer format 400 with an address field 401 and amemory corruption detection (MCD) value field 403 according toembodiments of the disclosure. In one embodiment, MCD value field 403 isto store the MCD value for the pointer, e.g., where the MCD value andthe address for the pointer are returned by the memory allocationroutine to the application that requested the memory allocation. MCDvalue field 403 may be located at any position (e.g., location) in thepointer, e.g., it is not fixed in one position. MCD value field 403 mayhave a size of 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 bits, etc. In oneembodiment, the MCD value field is not in the 1, 2, 3, 4, 5, 6, 7, 8, 9,10, etc. most significant bits or least significant bits of the pointer.In one embodiment, the position of the memory corruption detection valuein the pointer is selectable between a first location and a second,different location. In one embodiment, the position of the memorycorruption detection value in the pointer is selectable between a firstlocation, a second, different location, and a third, different location.In one embodiment, the position of the memory corruption detection valuein the pointer is selectable between a first location, a second,different location, a third different location, and fourth, differentlocation, etc. In one embodiment, a plurality of different locationsincludes one or more bit positions that do not overlap. In oneembodiment, a plurality of different locations includes one or more bitpositions that overlap.

FIG. 5 illustrates a pointer format 500 with an address field 501, amemory corruption detection (MCD) protected space field 505, and amemory corruption detection (MCD) value field 503 according toembodiments of the disclosure. In one embodiment, address field 501 is alinear address of the data line storing the data to be accessed. In oneembodiment, MCD value field 503 is to store the MCD value for thepointer. In one embodiment, MCD protected space field 505 stores a valueto indicate if the pointer is to a region of the memory that is to havea MCD validation check performed.

In one embodiment, the position of the memory corruption detection valuein each pointer is selectable, for example, at manufacture, at set-up,or by an application (e.g., software, such as, but not limited to, anoperating system), e.g., during activation of an MCD feature. Theposition may be set in the hardware processor, e.g., by writing to acontrol (or configuration) register. In one embodiment, the MCDprotected space (e.g., which subset(s) of the memory is protected by theMCD features) is selectable, for example, at manufacture, at set-up, orby an application (e.g., software, such as, but not limited to, anoperating system), e.g., during activation of an MCD feature. Theprotected space (e.g., less than all of the (addressable) memory) may beset in the hardware processor, e.g., by writing to a control (orconfiguration) register. In one embodiment, MCD hardware and methods,for example, via an ISA interface, allows the definition of one of moreof the following, e.g., by software (e.g. OS): (1) the position of theMCD value (e.g., metadata) in the pointer, e.g., which bits out of thelinear address in the pointer are used to store the MCD value, (2) theMCD protected space (e.g., range) to define the subset of memory (e.g.,addresses) that is to go through memory corruption detection (e.g., andthe address lines in memory that will have an MCD value), for example,the MCD protected space may be the linear address bits prefix thatdefines the protected region or memory range that is to go throughmemory corruption detection (e.g., and contains MCD value), and (3) apointer (e.g., linear address pointer) to the base of the memory MCD(e.g., metadata) table(s). In one embodiment, multiple subsets (e.g.,regions) of memory may be protected by MCD, for example, by havingmultiple attributes sets including the information above. In oneembodiment, these attributes may be implemented (e.g., set) through aregister (e.g., a control and/or configuration register).

In one embodiment, the following pseudocode in Table 1 below may be usedto check if a linear address in a pointer is part of an MCD protectedspace (e.g., such that MCD validation check is to be performed).

TABLE 1 LA_Prefix = LA[63:(MCD.Position+6)] If (MCD.Enabled &&MCD.Prefix == LA_Prefix)  MCD Check LA against MCD.MemoryMetadataTable

In one embodiment, there are multiple regions (e.g., [i] with adifferent index i for each region) and each region to be protected byMCD may be defined by one or more of: MCD[i].Enabled, MCD[i].Position,MCD[i].ProtectedSpace (e.g., MCD[i].Prefix), and MCD[i].BaseAddressOfMCDTable. In one embodiment, an (e.g., arbitrary) order forMCD protected space may be as in the following pseudocode in Table 2 forN protected regions.

TABLE 2 For i=1 to N LA_Prefix = LA[63:(MCD[i].Position+6)] If(MCD[i].Enabled && MCD[i].Prefix == LA_Prefix)  MCD Check againstMCD[i].MemoryMetadataTable  BreakAs noted above, the MCD value being 6 bits wide is merely an example andother sizes may be utilized.

FIG. 6 illustrates data formats of registers 608 for memory corruptiondetection (MCD) according to embodiments of the disclosure. Although tworegister are depicted, one or more registers may be utilized. In oneembodiment, a control or configuration register may be a model specificregister (MSR). MCD configuration register (CFG MSR) 620 may include oneor more of the following: a memory corruption detection (MCD) protectedspace field 622 (e.g., to set which subset of memory is to be protectedby the MCD hardware and/or methods disclosed herein), size field 626(e.g., to set the size (for example, number of bit positions) that anMCD value in the pointer and/or in an MCD table will include), andposition field 628 (e.g., to set which bits in the pointer are to beused as the MCD value, for example, the first bit position or last bitposition of the MCD value. In one embodiment, one or more fields (e.g.,reserved field 624) may not be used for MCD. MCD control register (CTRLMSR) 630 may include one or more of the following: base address of anMCD table field 632 (e.g., where a base address plus an offset (forexample, an offset from the address of the line(s) from the pointer)indicates a MCD value for a corresponding line in memory) and an enablefield 638 (e.g., MCD checking is enabled when set (e.g., to 1)). In oneembodiment, one or more fields (e.g., reserved field 634) are not usedfor MCD. In one embodiment, a reserved field (e.g., reserved field 624and/or reserved field 634) is used to define different modes for thebehavior of MCD validation. Although the bit positions (e.g., sizes) arelisted, these are example embodiments and other bit positions (e.g.,sizes) may be used in certain embodiments, for example, and may also befixed (e.g., constant and not configurable) in some embodiments. In oneembodiment, one or more of the above fields may be included in a singleregister or each field may be in its own register.

A write (e.g., store instruction) to a register may set one or more ofthe fields, e.g., a write from software to enable and/or set-up MCDprotection. A plurality of sets of MCD configuration and/or controlregisters may be utilized, for example, MCD CFG MSR [i] and MCD CTRL MSR[i], e.g., where i may be any positive integer. In one embodiment, adifferent value of i exists for each subset (e.g., region) of memory tobe protected by MCD, for example, wherein each subset (e.g., region) mayhave a different MCD table (e.g., and thus base address) and/ordifferent size, position, protected space, combinations thereof, etc.

FIG. 7 illustrates a memory corruption detection (MCD) system 700 with amemory management unit 706 according to embodiments of the disclosure.In the depicted embodiment, memory management unit 706 (e.g., memorymanagement circuit) is to receive the features that will be enabled(e.g., from a configuration and/or control register), for example, theposition of the MCD value in a pointer and/or the location of the MCDtable for the lines in memory. In the depicted embodiment, memorymanagement unit 706 is to receive a pointer (e.g., for a memory accessrequest). In one embodiment, the memory management unit 706 may performa linear address translation on the address value from the pointer todetermine the linear address of the line of memory pointed to by thepointer. In one embodiment, the memory management unit 706 removes a MCDvalue in the pointer from the linear address. In one embodiment, thememory management unit inserts a value into the removed MCD value bitpositions. For example, all the removed bits from the removed MCD valuemay be replaced by all zeros or all ones, e.g., matching the value ofthe most significant bit (e.g., bit position 63) of the pointer. Thelinear address without the MCD value may be utilized to obtain (e.g.,from the MCD table 716) the associated MCD value for the line of memory710. The MCD value in the pointer may then be compared to the MCD valuein the table for that line being pointed to for a determination if thereis a match (e.g., by the memory management unit 706). In certainembodiments, if the MCD values match, the data request is fulfilled. Incertain embodiments, if MCD values do not match, the data request isdenied.

FIG. 8 illustrates a memory management unit 806 according to embodimentsof the disclosure. In the depicted circuit in FIG. 8 , hardwarecomparator 840 is to compare the MCD protected space value (e.g., withthe example being bit positions 63:(X+6) of the configuration register(e.g., CFG MSR 620 in FIG. 6 )) with the same bit positions (e.g.,63:(X+6)) of the pointer (e.g., the linear address prefix value in theMCD protected space field in the pointer in FIG. 5 ). In the depictedembodiment, if the output of the comparator is true (e.g., 1 in binary)and the MCD enable bit is enabled (e.g., enable field 638 in CTRL MSR630 in FIG. 6 is set to 1 in binary), the logical AND gate 842 mayoutput a signal (e.g., 1 in binary). The 1 therefrom may be the controlsignal to multiplexer 844 and thus cause an output of the pointer (e.g.,the linear address) with the MCD value of the pointer removed therefrom.In the depicted embodiment, each of the removed MCD value bits arereplaced by the value in the most significant bit position (bit position63) of the pointer. A zero as a control signal to the multiplexer 844may cause an output of the original pointer (e.g., for a non MCDprotected region). A 1 output from the logical AND gate 842 may causethe logical AND gate 848 to output the results of the logical exclusiveOR (XOR) gate 846 on the MCD value from the pointer (e.g., (X+5):X) andthe number of bits in the MCD value in the pointer times the bit valuefrom bit 63. In one embodiment, this is to output the MCD value. In oneembodiment for canonical pointers (e.g., pointers where all of thecanonical bits are identical), the XOR gate 846 is to output an MCDvalue of 0. In an embodiment in reference to FIG. 16 , the MCD valuefield is stored in some of the canonical bits (62:57) and without MCD,all of those bits are to be 0 and with MCD, if those bits are 0 it meansthe MCD value is 0. In one embodiment in reference to FIG. 16 , wherebit 63 is a 1 without MCD, all of those bits are to be canonical (e.g.,bits 63:56=1) and with MCD, if bits 62:57 are 1, then XORing them withbit 63 will also result with an MCD value of 0. In one embodiment, thiscauses all canonical pointers to have an MCD value of 0, e.g., which maybe beneficial in software implementations. A zero to logical AND gate848 is to cause an output of zero. A 1 from the logical AND gate 842 maybe output as a signal that the input pointer is pointing to a line ofmemory that is in an MCD protected space. A 0 from the logical AND gate842 may be output as a signal that the input pointer is pointing to aline of memory that is not in an MCD protected space. Note that 6 is anexample bit size of the MCD value and other sizes may be used.

The following discusses examples of the number of lines that a pointerof a certain size may uniquely identify, e.g., a 57 bit linear addressmay allow unique pointers to 128 petabytes (PB).

FIG. 9 illustrates a pointer format 900 with an address field 901 andwithout a memory corruption detection (MCD) value field according toembodiments of the disclosure. For example, a 5-level paging operatingsystem (OS) may support 57 bit linear addresses in address field 901(e.g., out of 64 bits of space in the pointer 900). The remaining sevenupper (e.g., most significant) linear bits may be canonical (e.g., suchthat all bits 63:57 have the same value as bit 56).

FIG. 10 illustrates a pointer format 1000 with an address field 1001 andwithout a memory corruption detection (MCD) value field according toembodiments of the disclosure. For example, an OS may give a softwareapplication the positive linear address space (e.g., bits 63:56 equal to0) and reserve the negative linear address space (e.g., bits 63:56 equalto 1) for its own usage.

FIG. 11 illustrates a pointer format 1100 with an address field 1101, amemory corruption detection (MCD) protected space field in bits 63:56,and a memory corruption detection (MCD) value field 1103 according toembodiments of the disclosure. For example, in an embodiment with MCDprotection for the application linear address space and still remaininginside the canonical address range, the following attributes may be set(e.g., in a register(s)): MCD.Enabled=True, MCD.Position=50, andMCD.Prefix=00000000.

FIG. 12A illustrates a linear address space 1200 according toembodiments of the disclosure. Depicted linear address space 1200 may bethe entire linear address space that is addressable (e.g., by an OS).Depicted linear address space 1200 includes the negative canonicallinear address space 1250, the positive canonical linear address space1258, the positive non-canonical linear address space 1256, and thenegative non-canonical linear address space 1254. In one embodiment, thenon-canonical linear address space 1252 includes the addresses wherebits 63:57 do not each equal bit 56.

FIG. 12B illustrates a view of a portion of the linear address space1200 in FIG. 12A according to embodiments of the disclosure. Moreparticularly, FIG. 12B is a zoomed-in view of the positive linearaddress space (1256 and 1258).

FIG. 12C illustrates a view of the portion of the linear address space1200 in FIG. 12B with a subset of memory corruption detection (MCD)protected space 1260 according to embodiments of the disclosure. In oneembodiment, MCD protected space 1260 is 63 petabytes of positivecanonical linear address space out of the 64 petabytes of positivecanonical linear address space 1258, e.g., leaving 1 petabyte ofpositive non-canonical linear address space 1262 not protected by MCD.

FIG. 13 illustrates a pointer format 1300 with an address field 1301 andwithout a memory corruption detection (MCD) value field according toembodiments of the disclosure. For example, MCD may be used (e.g., by anOS) to protect a subset of linear address space inside its whole addressspace. In one embodiment, an OS may reserve the negative address rangefor its own usage, e.g., as shown in FIG. 13 with bits 63:56 equal to 1.

FIG. 14 illustrates a pointer format 1400 with an address field 1401, amemory corruption detection (MCD) protected space field 1405 (e.g., andbits 63:56), and a memory corruption detection (MCD) value field 1403according to embodiments of the disclosure. For example, in anembodiment with MCD protection for a subset of the OS linear addressspace, the following attributes may be set (e.g., in a register(s)):MCD.Enabled=True, MCD.Position=41, and MCD.Prefix=11111111XXXXXXXXX(e.g., where XXXXXXXX is a specific 9-bit value that defines which areaof the negative linear address space is MCD protected).

FIG. 15A illustrates a linear address space 1500 according toembodiments of the disclosure. Depicted linear address space 1500 may bethe entire linear address space that is addressable (e.g., by an OS).Depicted linear address space 1500 includes the negative canonicallinear address space 1550, the positive canonical linear address space1558, the positive non-canonical linear address space 1556, and thenegative non-canonical linear address space 1554. In one embodiment, thenon-canonical linear address space 1552 includes the addresses wherebits 63:57 do not each equal bit 56.

FIG. 15B illustrates a view of a portion of the linear address space1500 in FIG. 15A according to embodiments of the disclosure. Moreparticularly, FIG. 15B is a zoomed-in view of the negative canonicallinear address space 1550.

FIG. 15C illustrates a view of the portion of the linear address space1500 in FIG. 15B with a subset of memory corruption detection (MCD)protected space 1560 according to embodiments of the disclosure. In oneembodiment, MCD protected space 1560 is 128 terabytes of availablelinear address space out of the 64 petabytes of negative canonicallinear address space 1550. In one embodiment, MCD protected spacesection 1560A and MCD protected space section 1560B combined contain theentire address range that matches the MCD.Prefix value (e.g.,111111XXXXXXXXX). In one embodiment, MCD protected space section 1560Bare the addresses where a pointer's MCD value is not 0 (e.g., the sameas the MCD protected space 1260 in FIG. 12C). In one embodiment, MCDprotected space section 1560A are the addresses where the pointer MCDvalue is 0 (e.g., the same as space 1262 in FIG. 12C). In certainembodiments, all addresses that reside in MCD protected space section1560B are transformed (e.g., according to the circuit in FIG. 8 ) andthe actual memory operation is to go to the addresses that are in MCDprotected space section 1560A.

FIG. 16 illustrates a pointer format 1600 with an address field 1601, amemory corruption detection (MCD) space field, and a memory corruptiondetection (MCD) value field 1603 according to embodiments of thedisclosure. For example, the following attributes may be set (e.g., in aregister(s)): MCD.Enabled=True, MCD.Position=57, and MCD.Prefix=0.

FIG. 17A illustrates a linear address space 1700 according toembodiments of the disclosure. Depicted linear address space 1700 may bethe entire linear address space that is addressable (e.g., by an OS).Depicted linear address space 1700 includes the negative canonicallinear address space 1750, the positive canonical linear address space1758, the positive non-canonical linear address space 1756, and thenegative non-canonical linear address space 1754. In one embodiment, thenon-canonical linear address space 1752 includes the addresses wherebits 63:57 do not each equal bit 56.

FIG. 17B illustrates a view of a portion of the linear address space1700 in FIG. 17A according to embodiments of the disclosure. Moreparticularly, FIG. 17B is a zoomed-in view of the positive linearaddress space (1758 and 1756).

FIG. 17C illustrates a view of the portion of the linear address space1700 in FIG. 17B with a subset of memory corruption detection (MCD)protected space in the positive, non-canonical linear address space 1756according to embodiments of the disclosure. In one embodiment, MCDprotected space is in alternating sections, e.g., in positive,non-canonical linear address space 1756. In one embodiment, the MCDvalue in a pointer is in the canonical bits (62:57), but bit 63 is(e.g., be required to be) canonical and equal to bit 56. In oneembodiment, this means that the addresses where bit 63 is equal to bit56 are the MCD protected space and the addresses where bit 63 is notequal to bit 56 are non-canonical. In the depicted embodiment, each MCDprotected space section (e.g., box) is the size of address space 1758,but is compressed to illustrate them in this figure.

FIG. 18 illustrates a flow diagram 1800 according to embodiments of thedisclosure. Flow diagram 1800 includes receiving a request to access ablock of a memory through a pointer to the block of the memory 1802, andallowing access to the block of the memory when a memory corruptiondetection value in the pointer is validated with a memory corruptiondetection value in the memory for the block, wherein a position of thememory corruption detection value in the pointer is selectable between afirst location and a second, different location 1804.

In one embodiment, a hardware processor includes an execution unit toexecute an instruction to request access to a block of a memory througha pointer to the block of the memory, and a memory management unit toallow access to the block of the memory when a memory corruptiondetection value in the pointer is validated with a memory corruptiondetection value in the memory for the block, wherein a position of thememory corruption detection value in the pointer is selectable between afirst location and a second, different location. The hardware processormay include a control register to set the position to the first locationor the second, different location. The hardware processor may include acontrol register to set a memory corruption detection protected spacefor a subset of the memory. The pointer may include a memory corruptiondetection protected space value, and the memory management unit mayallow access to the block of the memory without a validation check ofthe memory corruption detection value in the pointer with the memorycorruption detection value in the memory for the block when the memorycorruption detection protected space value is not within the memorycorruption detection protected space for the subset of the memory. Thepointer may include a memory corruption detection protected space value,and the memory management unit may perform a validation check of thememory corruption detection value in the pointer with the memorycorruption detection value in the memory for the block when the memorycorruption detection protected space value is within the memorycorruption detection protected space for the subset of the memory. Thehardware processor may include a register to store a base address of amemory corruption detection table in the memory comprising the memorycorruption detection value for the block. The position of the memorycorruption detection value in the pointer may be selectable between thefirst location, the second, different location, and a third, differentlocation. The pointer may include a linear address of the block of thememory.

In another embodiment, a method includes receiving a request to access ablock of a memory through a pointer to the block of the memory, andallowing access to the block of the memory when a memory corruptiondetection value in the pointer is validated with a memory corruptiondetection value in the memory for the block, wherein a position of thememory corruption detection value in the pointer is selectable between afirst location and a second, different location. The method may includesetting the position to the first location or the second, differentlocation. The method may include setting a memory corruption detectionprotected space for a subset of the memory. The pointer may include amemory corruption detection protected space value, and the method mayinclude allowing access to the block of the memory without a validationcheck of the memory corruption detection value in the pointer with thememory corruption detection value in the memory for the block when thememory corruption detection protected space value is not within thememory corruption detection protected space for the subset of thememory. The pointer may include a memory corruption detection protectedspace value, and the method may include performing a validation check ofthe memory corruption detection value in the pointer with the memorycorruption detection value in the memory for the block when the memorycorruption detection protected space value is within the memorycorruption detection protected space for the subset of the memory. Themethod may include storing a base address of a memory corruptiondetection table in the memory comprising the memory corruption detectionvalue for the block. The position of the memory corruption detectionvalue in the pointer may be selectable between the first location, thesecond, different location, and a third, different location. The pointermay include a linear address of the block of the memory.

In yet another embodiment, a system includes a memory, a hardwareprocessor comprising an execution unit to execute an instruction torequest access to a block of the memory through a pointer to the blockof the memory, and a memory management unit to allow access to the blockof the memory when a memory corruption detection value in the pointer isvalidated with a memory corruption detection value in the memory for theblock, wherein a position of the memory corruption detection value inthe pointer is selectable between a first location and a second,different location. The system may include a control register to set theposition to the first location or the second, different location. Thesystem may include a control register to set a memory corruptiondetection protected space for a subset of the memory. The pointer mayinclude a memory corruption detection protected space value, and thememory management unit may allow access to the block of the memorywithout a validation check of the memory corruption detection value inthe pointer with the memory corruption detection value in the memory forthe block when the memory corruption detection protected space value isnot within the memory corruption detection protected space for thesubset of the memory. The pointer may include a memory corruptiondetection protected space value, and the memory management unit mayperform a validation check of the memory corruption detection value inthe pointer with the memory corruption detection value in the memory forthe block when the memory corruption detection protected space value iswithin the memory corruption detection protected space for the subset ofthe memory. The system may include a register to store a base address ofa memory corruption detection table in the memory comprising the memorycorruption detection value for the block. The position of the memorycorruption detection value in the pointer may be selectable between thefirst location, the second, different location, and a third, differentlocation. The pointer may include a linear address of the block of thememory.

In another embodiment, a hardware processor includes means to execute aninstruction to request access to a block of a memory through a pointerto the block of the memory, and means to allow access to the block ofthe memory when a memory corruption detection value in the pointer isvalidated with a memory corruption detection value in the memory for theblock, wherein a position of the memory corruption detection value inthe pointer is selectable between a first location and a second,different location.

In yet another embodiment, an apparatus comprises a data storage devicethat stores code that when executed by a hardware processor causes thehardware processor to perform any method disclosed herein. An apparatusmay be as described in the detailed description. A method may be asdescribed in the detailed description.

An instruction set may include one or more instruction formats. A giveninstruction format may define various fields (e.g., number of bits,location of bits) to specify, among other things, the operation to beperformed (e.g., opcode) and the operand(s) on which that operation isto be performed and/or other data field(s) (e.g., mask). Someinstruction formats are further broken down though the definition ofinstruction templates (or subformats). For example, the instructiontemplates of a given instruction format may be defined to have differentsubsets of the instruction format's fields (the included fields aretypically in the same order, but at least some have different bitpositions because there are less fields included) and/or defined to havea given field interpreted differently. Thus, each instruction of an ISAis expressed using a given instruction format (and, if defined, in agiven one of the instruction templates of that instruction format) andincludes fields for specifying the operation and the operands. Forexample, an exemplary ADD instruction has a specific opcode and aninstruction format that includes an opcode field to specify that opcodeand operand fields to select operands (source1/destination and source2);and an occurrence of this ADD instruction in an instruction stream willhave specific contents in the operand fields that select specificoperands. A set of SIMD extensions referred to as the Advanced VectorExtensions (AVX) (AVX1 and AVX2) and using the Vector Extensions (VEX)coding scheme has been released and/or published (e.g., see Intel® 64and IA-32 Architectures Software Developer's Manual, September 2015; andsee Intel® Architecture Instruction Set Extensions ProgrammingReference, August 2015).

Exemplary Core Architectures, Processors, and Computer Architectures

Processor cores may be implemented in different ways, for differentpurposes, and in different processors. For instance, implementations ofsuch cores may include: 1) a general purpose in-order core intended forgeneral-purpose computing; 2) a high performance general purposeout-of-order core intended for general-purpose computing; 3) a specialpurpose core intended primarily for graphics and/or scientific(throughput) computing. Implementations of different processors mayinclude: 1) a CPU including one or more general purpose in-order coresintended for general-purpose computing and/or one or more generalpurpose out-of-order cores intended for general-purpose computing; and2) a coprocessor including one or more special purpose cores intendedprimarily for graphics and/or scientific (throughput). Such differentprocessors lead to different computer system architectures, which mayinclude: 1) the coprocessor on a separate chip from the CPU; 2) thecoprocessor on a separate die in the same package as a CPU; 3) thecoprocessor on the same die as a CPU (in which case, such a coprocessoris sometimes referred to as special purpose logic, such as integratedgraphics and/or scientific (throughput) logic, or as special purposecores); and 4) a system on a chip that may include on the same die thedescribed CPU (sometimes referred to as the application core(s) orapplication processor(s)), the above described coprocessor, andadditional functionality. Exemplary core architectures are describednext, followed by descriptions of exemplary processors and computerarchitectures.

Exemplary Core Architectures In-Order and Out-of-Order Core BlockDiagram

FIG. 19A is a block diagram illustrating both an exemplary in-orderpipeline and an exemplary register renaming, out-of-orderissue/execution pipeline according to embodiments of the disclosure.FIG. 19B is a block diagram illustrating both an exemplary embodiment ofan in-order architecture core and an exemplary register renaming,out-of-order issue/execution architecture core to be included in aprocessor according to embodiments of the disclosure. The solid linedboxes in FIGS. 19A-B illustrate the in-order pipeline and in-order core,while the optional addition of the dashed lined boxes illustrates theregister renaming, out-of-order issue/execution pipeline and core. Giventhat the in-order aspect is a subset of the out-of-order aspect, theout-of-order aspect will be described.

In FIG. 19A, a processor pipeline 1900 includes a fetch stage 1902, alength decode stage 1904, a decode stage 1906, an allocation stage 1908,a renaming stage 1910, a scheduling (also known as a dispatch or issue)stage 1912, a register read/memory read stage 1914, an execute stage1916, a write back/memory write stage 1918, an exception handling stage1922, and a commit stage 1924.

FIG. 19B shows processor core 1990 including a front end unit 1930coupled to an execution engine unit 1950, and both are coupled to amemory unit 1970. The core 1990 may be a reduced instruction setcomputing (RISC) core, a complex instruction set computing (CISC) core,a very long instruction word (VLIW) core, or a hybrid or alternativecore type. As yet another option, the core 1990 may be a special-purposecore, such as, for example, a network or communication core, compressionengine, coprocessor core, general purpose computing graphics processingunit (GPGPU) core, graphics core, or the like.

The front end unit 1930 includes a branch prediction unit 1932 coupledto an instruction cache unit 1934, which is coupled to an instructiontranslation lookaside buffer (TLB) 1936, which is coupled to aninstruction fetch unit 1938, which is coupled to a decode unit 1940. Thedecode unit 1940 (or decoder or decoder unit) may decode instructions(e.g., macro-instructions), and generate as an output one or moremicro-operations, micro-code entry points, micro-instructions, otherinstructions, or other control signals, which are decoded from, or whichotherwise reflect, or are derived from, the original instructions. Thedecode unit 1940 may be implemented using various different mechanisms.Examples of suitable mechanisms include, but are not limited to, look-uptables, hardware implementations, programmable logic arrays (PLAs),microcode read only memories (ROMs), etc. In one embodiment, the core1990 includes a microcode ROM or other medium that stores microcode forcertain macroinstructions (e.g., in decode unit 1940 or otherwise withinthe front end unit 1930). The decode unit 1940 is coupled to arename/allocator unit 1952 in the execution engine unit 1950.

The execution engine unit 1950 includes the rename/allocator unit 1952coupled to a retirement unit 1954 and a set of one or more schedulerunit(s) 1956. The scheduler unit(s) 1956 represents any number ofdifferent schedulers, including reservations stations, centralinstruction window, etc. The scheduler unit(s) 1956 is coupled to thephysical register file(s) unit(s) 1958. Each of the physical registerfile(s) units 1958 represents one or more physical register files,different ones of which store one or more different data types, such asscalar integer, scalar floating point, packed integer, packed floatingpoint, vector integer, vector floating point, status (e.g., aninstruction pointer that is the address of the next instruction to beexecuted), etc. In one embodiment, the physical register file(s) unit1958 comprises a vector registers unit, a write mask registers unit, anda scalar registers unit. These register units may provide architecturalvector registers, vector mask registers, and general purpose registers.The physical register file(s) unit(s) 1958 is overlapped by theretirement unit 1954 to illustrate various ways in which registerrenaming and out-of-order execution may be implemented (e.g., using areorder buffer(s) and a retirement register file(s); using a futurefile(s), a history buffer(s), and a retirement register file(s); using aregister maps and a pool of registers; etc.). The retirement unit 1954and the physical register file(s) unit(s) 1958 are coupled to theexecution cluster(s) 1960. The execution cluster(s) 1960 includes a setof one or more execution units 1962 and a set of one or more memoryaccess units 1964. The execution units 1962 may perform variousoperations (e.g., shifts, addition, subtraction, multiplication) and onvarious types of data (e.g., scalar floating point, packed integer,packed floating point, vector integer, vector floating point). Whilesome embodiments may include a number of execution units dedicated tospecific functions or sets of functions, other embodiments may includeonly one execution unit or multiple execution units that all perform allfunctions. The scheduler unit(s) 1956, physical register file(s) unit(s)1958, and execution cluster(s) 1960 are shown as being possibly pluralbecause certain embodiments create separate pipelines for certain typesof data/operations (e.g., a scalar integer pipeline, a scalar floatingpoint/packed integer/packed floating point/vector integer/vectorfloating point pipeline, and/or a memory access pipeline that each havetheir own scheduler unit, physical register file(s) unit, and/orexecution cluster—and in the case of a separate memory access pipeline,certain embodiments are implemented in which only the execution clusterof this pipeline has the memory access unit(s) 1964). It should also beunderstood that where separate pipelines are used, one or more of thesepipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units 1964 is coupled to the memory unit 1970,which includes a data TLB unit 1972 coupled to a data cache unit 1974coupled to a level 2 (L2) cache unit 1976. In one exemplary embodiment,the memory access units 1964 may include a load unit, a store addressunit, and a store data unit, each of which is coupled to the data TLBunit 1972 in the memory unit 1970. The instruction cache unit 1934 isfurther coupled to a level 2 (L2) cache unit 1976 in the memory unit1970. The L2 cache unit 1976 is coupled to one or more other levels ofcache and eventually to a main memory.

By way of example, the exemplary register renaming, out-of-orderissue/execution core architecture may implement the pipeline 1900 asfollows: 1) the instruction fetch 1938 performs the fetch and lengthdecoding stages 1902 and 1904; 2) the decode unit 1940 performs thedecode stage 1906; 3) the rename/allocator unit 1952 performs theallocation stage 1908 and renaming stage 1910; 4) the scheduler unit(s)1956 performs the schedule stage 1912; 5) the physical register file(s)unit(s) 1958 and the memory unit 1970 perform the register read/memoryread stage 1914; the execution cluster 1960 perform the execute stage1916; 6) the memory unit 1970 and the physical register file(s) unit(s)1958 perform the write back/memory write stage 1918; 7) various unitsmay be involved in the exception handling stage 1922; and 8) theretirement unit 1954 and the physical register file(s) unit(s) 1958perform the commit stage 1924.

The core 1990 may support one or more instructions sets (e.g., the x86instruction set (with some extensions that have been added with newerversions); the MIPS instruction set of MIPS Technologies of Sunnyvale,Calif.; the ARM instruction set (with optional additional extensionssuch as NEON) of ARM Holdings of Sunnyvale, Calif.), including theinstruction(s) described herein. In one embodiment, the core 1990includes logic to support a packed data instruction set extension (e.g.,AVX1, AVX2), thereby allowing the operations used by many multimediaapplications to be performed using packed data.

It should be understood that the core may support multithreading(executing two or more parallel sets of operations or threads), and maydo so in a variety of ways including time sliced multithreading,simultaneous multithreading (where a single physical core provides alogical core for each of the threads that physical core issimultaneously multithreading), or a combination thereof (e.g., timesliced fetching and decoding and simultaneous multithreading thereaftersuch as in the Intel® Hyperthreading technology).

While register renaming is described in the context of out-of-orderexecution, it should be understood that register renaming may be used inan in-order architecture. While the illustrated embodiment of theprocessor also includes separate instruction and data cache units1934/1974 and a shared L2 cache unit 1976, alternative embodiments mayhave a single internal cache for both instructions and data, such as,for example, a Level 1 (L1) internal cache, or multiple levels ofinternal cache. In some embodiments, the system may include acombination of an internal cache and an external cache that is externalto the core and/or the processor. Alternatively, all of the cache may beexternal to the core and/or the processor.

Specific Exemplary In-Order Core Architecture

FIGS. 20A-B illustrate a block diagram of a more specific exemplaryin-order core architecture, which core would be one of several logicblocks (including other cores of the same type and/or different types)in a chip. The logic blocks communicate through a high-bandwidthinterconnect network (e.g., a ring network) with some fixed functionlogic, memory I/O interfaces, and other necessary I/O logic, dependingon the application.

FIG. 20A is a block diagram of a single processor core, along with itsconnection to the on-die interconnect network 2002 and with its localsubset of the Level 2 (L2) cache 2004, according to embodiments of thedisclosure. In one embodiment, an instruction decode unit 2000 supportsthe x86 instruction set with a packed data instruction set extension. AnL1 cache 2006 allows low-latency accesses to cache memory into thescalar and vector units. While in one embodiment (to simplify thedesign), a scalar unit 2008 and a vector unit 2010 use separate registersets (respectively, scalar registers 2012 and vector registers 2014) anddata transferred between them is written to memory and then read back infrom a level 1 (L1) cache 2006, alternative embodiments of thedisclosure may use a different approach (e.g., use a single register setor include a communication path that allow data to be transferredbetween the two register files without being written and read back).

The local subset of the L2 cache 2004 is part of a global L2 cache thatis divided into separate local subsets, one per processor core. Eachprocessor core has a direct access path to its own local subset of theL2 cache 2004. Data read by a processor core is stored in its L2 cachesubset 2004 and can be accessed quickly, in parallel with otherprocessor cores accessing their own local L2 cache subsets. Data writtenby a processor core is stored in its own L2 cache subset 2004 and isflushed from other subsets, if necessary. The ring network ensurescoherency for shared data. The ring network is bi-directional to allowagents such as processor cores, L2 caches and other logic blocks tocommunicate with each other within the chip. Each ring data-path is1012-bits wide per direction.

FIG. 20B is an expanded view of part of the processor core in FIG. 20Aaccording to embodiments of the disclosure. FIG. 20B includes an L1 datacache 2006A part of the L1 cache 2004, as well as more detail regardingthe vector unit 2010 and the vector registers 2014. Specifically, thevector unit 2010 is a 16-wide vector processing unit (VPU) (see the16-wide ALU 2028), which executes one or more of integer,single-precision float, and double-precision float instructions. The VPUsupports swizzling the register inputs with swizzle unit 2020, numericconversion with numeric convert units 2022A-B, and replication withreplication unit 2024 on the memory input. Write mask registers 2026allow predicating resulting vector writes.

FIG. 21 is a block diagram of a processor 2100 that may have more thanone core, may have an integrated memory controller, and may haveintegrated graphics according to embodiments of the disclosure. Thesolid lined boxes in FIG. 21 illustrate a processor 2100 with a singlecore 2102A, a system agent 2110, a set of one or more bus controllerunits 2116, while the optional addition of the dashed lined boxesillustrates an alternative processor 2100 with multiple cores 2102A-N, aset of one or more integrated memory controller unit(s) 2114 in thesystem agent unit 2110, and special purpose logic 2108.

Thus, different implementations of the processor 2100 may include: 1) aCPU with the special purpose logic 2108 being integrated graphics and/orscientific (throughput) logic (which may include one or more cores), andthe cores 2102A-N being one or more general purpose cores (e.g., generalpurpose in-order cores, general purpose out-of-order cores, acombination of the two); 2) a coprocessor with the cores 2102A-N being alarge number of special purpose cores intended primarily for graphicsand/or scientific (throughput); and 3) a coprocessor with the cores2102A-N being a large number of general purpose in-order cores. Thus,the processor 2100 may be a general-purpose processor, coprocessor orspecial-purpose processor, such as, for example, a network orcommunication processor, compression engine, graphics processor, GPGPU(general purpose graphics processing unit), a high-throughput manyintegrated core (MIC) coprocessor (including 30 or more cores), embeddedprocessor, or the like. The processor may be implemented on one or morechips. The processor 2100 may be a part of and/or may be implemented onone or more substrates using any of a number of process technologies,such as, for example, BiCMOS, CMOS, or NMOS.

The memory hierarchy includes one or more levels of cache within thecores, a set or one or more shared cache units 2106, and external memory(not shown) coupled to the set of integrated memory controller units2114. The set of shared cache units 2106 may include one or moremid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), orother levels of cache, a last level cache (LLC), and/or combinationsthereof. While in one embodiment a ring based interconnect unit 2112interconnects the integrated graphics logic 2108, the set of sharedcache units 2106, and the system agent unit 2110/integrated memorycontroller unit(s) 2114, alternative embodiments may use any number ofwell-known techniques for interconnecting such units. In one embodiment,coherency is maintained between one or more cache units 2106 and cores2102-A-N.

In some embodiments, one or more of the cores 2102A-N are capable ofmultithreading. The system agent 2110 includes those componentscoordinating and operating cores 2102A-N. The system agent unit 2110 mayinclude for example a power control unit (PCU) and a display unit. ThePCU may be or include logic and components needed for regulating thepower state of the cores 2102A-N and the integrated graphics logic 2108.The display unit is for driving one or more externally connecteddisplays.

The cores 2102A-N may be homogenous or heterogeneous in terms ofarchitecture instruction set; that is, two or more of the cores 2102A-Nmay be capable of execution the same instruction set, while others maybe capable of executing only a subset of that instruction set or adifferent instruction set.

Exemplary Computer Architectures

FIGS. 22-25 are block diagrams of exemplary computer architectures.Other system designs and configurations known in the arts for laptops,desktops, handheld PCs, personal digital assistants, engineeringworkstations, servers, network devices, network hubs, switches, embeddedprocessors, digital signal processors (DSPs), graphics devices, videogame devices, set-top boxes, micro controllers, cell phones, portablemedia players, hand held devices, and various other electronic devices,are also suitable. In general, a huge variety of systems or electronicdevices capable of incorporating a processor and/or other executionlogic as disclosed herein are generally suitable.

Referring now to FIG. 22 , shown is a block diagram of a system 2200 inaccordance with one embodiment of the present disclosure. The system2200 may include one or more processors 2210, 2215, which are coupled toa controller hub 2220. In one embodiment the controller hub 2220includes a graphics memory controller hub (GMCH) 2290 and anInput/Output Hub (IOH) 2250 (which may be on separate chips); the GMCH2290 includes memory and graphics controllers to which are coupledmemory 2240 and a coprocessor 2245; the IOH 2250 is couples input/output(I/O) devices 2260 to the GMCH 2290. Alternatively, one or both of thememory and graphics controllers are integrated within the processor (asdescribed herein), the memory 2240 and the coprocessor 2245 are coupleddirectly to the processor 2210, and the controller hub 2220 in a singlechip with the IOH 2250. Memory 2240 may include a memory corruptiondetection module 2240A, for example, to store code that when executedcauses a processor to perform any method of this disclosure. In anotherembodiment, memory corruption detection module 2240A resides inside aprocessor and communicates with memory 2240.

The optional nature of additional processors 2215 is denoted in FIG. 22with broken lines. Each processor 2210, 2215 may include one or more ofthe processing cores described herein and may be some version of theprocessor 2100.

The memory 2240 may be, for example, dynamic random access memory(DRAM), phase change memory (PCM), or a combination of the two. For atleast one embodiment, the controller hub 2220 communicates with theprocessor(s) 2210, 2215 via a multi-drop bus, such as a frontside bus(FSB), point-to-point interface such as QuickPath Interconnect (QPI), orsimilar connection 2295.

In one embodiment, the coprocessor 2245 is a special-purpose processor,such as, for example, a high-throughput MIC processor, a network orcommunication processor, compression engine, graphics processor, GPGPU,embedded processor, or the like. In one embodiment, controller hub 2220may include an integrated graphics accelerator.

There can be a variety of differences between the physical resources2210, 2215 in terms of a spectrum of metrics of merit includingarchitectural, microarchitectural, thermal, power consumptioncharacteristics, and the like.

In one embodiment, the processor 2210 executes instructions that controldata processing operations of a general type. Embedded within theinstructions may be coprocessor instructions. The processor 2210recognizes these coprocessor instructions as being of a type that shouldbe executed by the attached coprocessor 2245. Accordingly, the processor2210 issues these coprocessor instructions (or control signalsrepresenting coprocessor instructions) on a coprocessor bus or otherinterconnect, to coprocessor 2245. Coprocessor(s) 2245 accept andexecute the received coprocessor instructions.

Referring now to FIG. 23 , shown is a block diagram of a first morespecific exemplary system 2300 in accordance with an embodiment of thepresent disclosure. As shown in FIG. 23 , multiprocessor system 2300 isa point-to-point interconnect system, and includes a first processor2370 and a second processor 2380 coupled via a point-to-pointinterconnect 2350. Each of processors 2370 and 2380 may be some versionof the processor 2100. In one embodiment of the disclosure, processors2370 and 2380 are respectively processors 2210 and 2215, whilecoprocessor 2338 is coprocessor 2245. In another embodiment, processors2370 and 2380 are respectively processor 2210 coprocessor 2245.

Processors 2370 and 2380 are shown including integrated memorycontroller (IMC) units 2372 and 2382, respectively. Processor 2370 alsoincludes as part of its bus controller units point-to-point (P-P)interfaces 2376 and 2378; similarly, second processor 2380 includes P-Pinterfaces 2386 and 2388. Processors 2370, 2380 may exchange informationvia a point-to-point (P-P) interface 2350 using P-P interface circuits2378, 2388. As shown in FIG. 23 , IMCs 2372 and 2382 couple theprocessors to respective memories, namely a memory 2332 and a memory2334, which may be portions of main memory locally attached to therespective processors.

Processors 2370, 2380 may each exchange information with a chipset 2390via individual P-P interfaces 2352, 2354 using point to point interfacecircuits 2376, 2394, 2386, 2398. Chipset 2390 may optionally exchangeinformation with the coprocessor 2338 via a high-performance interface2339. In one embodiment, the coprocessor 2338 is a special-purposeprocessor, such as, for example, a high-throughput MIC processor, anetwork or communication processor, compression engine, graphicsprocessor, GPGPU, embedded processor, or the like.

A shared cache (not shown) may be included in either processor oroutside of both processors, yet connected with the processors via P-Pinterconnect, such that either or both processors' local cacheinformation may be stored in the shared cache if a processor is placedinto a low power mode.

Chipset 2390 may be coupled to a first bus 2316 via an interface 2396.In one embodiment, first bus 2316 may be a Peripheral ComponentInterconnect (PCI) bus, or a bus such as a PCI Express bus or anotherthird generation I/O interconnect bus, although the scope of the presentdisclosure is not so limited.

As shown in FIG. 23 , various I/O devices 2314 may be coupled to firstbus 2316, along with a bus bridge 2318 which couples first bus 2316 to asecond bus 2320. In one embodiment, one or more additional processor(s)2315, such as coprocessors, high-throughput MIC processors, GPGPU's,accelerators (such as, e.g., graphics accelerators or digital signalprocessing (DSP) units), field programmable gate arrays, or any otherprocessor, are coupled to first bus 2316. In one embodiment, second bus2320 may be a low pin count (LPC) bus. Various devices may be coupled toa second bus 2320 including, for example, a keyboard and/or mouse 2322,communication devices 2327 and a storage unit 2328 such as a disk driveor other mass storage device which may include instructions/code anddata 2330, in one embodiment. Further, an audio I/O 2324 may be coupledto the second bus 2320. Note that other architectures are possible. Forexample, instead of the point-to-point architecture of FIG. 23 , asystem may implement a multi-drop bus or other such architecture.

Referring now to FIG. 24 , shown is a block diagram of a second morespecific exemplary system 2400 in accordance with an embodiment of thepresent disclosure. Like elements in FIGS. 23 and 24 bear like referencenumerals, and certain aspects of FIG. 23 have been omitted from FIG. 24in order to avoid obscuring other aspects of FIG. 24 .

FIG. 24 illustrates that the processors 2370, 2380 may includeintegrated memory and I/O control logic (“CL”) 2372 and 2382,respectively. Thus, the CL 2372, 2382 include integrated memorycontroller units and include I/O control logic. FIG. 24 illustrates thatnot only are the memories 2332, 2334 coupled to the CL 2372, 2382, butalso that I/O devices 2414 are also coupled to the control logic 2372,2382. Legacy I/O devices 2415 are coupled to the chipset 2390.

Referring now to FIG. 25 , shown is a block diagram of a SoC 2500 inaccordance with an embodiment of the present disclosure. Similarelements in FIG. 21 bear like reference numerals. Also, dashed linedboxes are optional features on more advanced SoCs. In FIG. 25 , aninterconnect unit(s) 2502 is coupled to: an application processor 2510which includes a set of one or more cores 202A-N and shared cacheunit(s) 2106; a system agent unit 2110; a bus controller unit(s) 2116;an integrated memory controller unit(s) 2114; a set or one or morecoprocessors 2520 which may include integrated graphics logic, an imageprocessor, an audio processor, and a video processor; a static randomaccess memory (SRAM) unit 2530; a direct memory access (DMA) unit 2532;and a display unit 2540 for coupling to one or more external displays.In one embodiment, the coprocessor(s) 2520 include a special-purposeprocessor, such as, for example, a network or communication processor,compression engine, GPGPU, a high-throughput MIC processor, embeddedprocessor, or the like.

Embodiments (e.g., of the mechanisms) disclosed herein may beimplemented in hardware, software, firmware, or a combination of suchimplementation approaches. Embodiments of the disclosure may beimplemented as computer programs or program code executing onprogrammable systems comprising at least one processor, a storage system(including volatile and non-volatile memory and/or storage elements), atleast one input device, and at least one output device.

Program code, such as code 2330 illustrated in FIG. 23 , may be appliedto input instructions to perform the functions described herein andgenerate output information. The output information may be applied toone or more output devices, in known fashion. For purposes of thisapplication, a processing system includes any system that has aprocessor, such as, for example; a digital signal processor (DSP), amicrocontroller, an application specific integrated circuit (ASIC), or amicroprocessor.

The program code may be implemented in a high level procedural or objectoriented programming language to communicate with a processing system.The program code may also be implemented in assembly or machinelanguage, if desired. In fact, the mechanisms described herein are notlimited in scope to any particular programming language. In any case,the language may be a compiled or interpreted language.

One or more aspects of at least one embodiment may be implemented byrepresentative instructions stored on a machine-readable medium whichrepresents various logic within the processor, which when read by amachine causes the machine to fabricate logic to perform the techniquesdescribed herein. Such representations, known as “IP cores,” may bestored on a tangible, machine readable medium and supplied to variouscustomers or manufacturing facilities to load into the fabricationmachines that actually make the logic or processor.

Such machine-readable storage media may include, without limitation,non-transitory, tangible arrangements of articles manufactured or formedby a machine or device, including storage media such as hard disks, anyother type of disk including floppy disks, optical disks, compact diskread-only memories (CD-ROMs), compact disk rewritables (CD-RWs), andmagneto-optical disks, semiconductor devices such as read-only memories(ROMs), random access memories (RAMs) such as dynamic random accessmemories (DRAMs), static random access memories (SRAMs), erasableprogrammable read-only memories (EPROMs), flash memories, electricallyerasable programmable read-only memories (EEPROMs), phase change memory(PCM), magnetic or optical cards, or any other type of media suitablefor storing electronic instructions.

Accordingly, embodiments of the disclosure also include non-transitory,tangible machine-readable media containing instructions or containingdesign data, such as Hardware Description Language (HDL), which definesstructures, circuits, apparatuses, processors and/or system featuresdescribed herein. Such embodiments may also be referred to as programproducts.

Emulation (Including Binary Translation, Code Morphing, Etc.)

In some cases, an instruction converter may be used to convert aninstruction from a source instruction set to a target instruction set.For example, the instruction converter may translate (e.g., using staticbinary translation, dynamic binary translation including dynamiccompilation), morph, emulate, or otherwise convert an instruction to oneor more other instructions to be processed by the core. The instructionconverter may be implemented in software, hardware, firmware, or acombination thereof. The instruction converter may be on processor, offprocessor, or part on and part off processor.

FIG. 26 is a block diagram contrasting the use of a software instructionconverter to convert binary instructions in a source instruction set tobinary instructions in a target instruction set according to embodimentsof the disclosure. In the illustrated embodiment, the instructionconverter is a software instruction converter, although alternativelythe instruction converter may be implemented in software, firmware,hardware, or various combinations thereof. FIG. 26 shows a program in ahigh level language 2602 may be compiled using an x86 compiler 2604 togenerate x86 binary code 2606 that may be natively executed by aprocessor with at least one x86 instruction set core 2616. The processorwith at least one x86 instruction set core 2616 represents any processorthat can perform substantially the same functions as an Intel processorwith at least one x86 instruction set core by compatibly executing orotherwise processing (1) a substantial portion of the instruction set ofthe Intel x86 instruction set core or (2) object code versions ofapplications or other software targeted to run on an Intel processorwith at least one x86 instruction set core, in order to achievesubstantially the same result as an Intel processor with at least onex86 instruction set core. The x86 compiler 2604 represents a compilerthat is operable to generate x86 binary code 2606 (e.g., object code)that can, with or without additional linkage processing, be executed onthe processor with at least one x86 instruction set core 2616.Similarly, FIG. 26 shows the program in the high level language 2602 maybe compiled using an alternative instruction set compiler 2608 togenerate alternative instruction set binary code 2610 that may benatively executed by a processor without at least one x86 instructionset core 2614 (e.g., a processor with cores that execute the MIPSinstruction set of MIPS Technologies of Sunnyvale, Calif. and/or thatexecute the ARM instruction set of ARM Holdings of Sunnyvale, Calif.).The instruction converter 2612 is used to convert the x86 binary code2606 into code that may be natively executed by the processor without anx86 instruction set core 2614. This converted code is not likely to bethe same as the alternative instruction set binary code 2610 because aninstruction converter capable of this is difficult to make; however, theconverted code will accomplish the general operation and be made up ofinstructions from the alternative instruction set. Thus, the instructionconverter 2612 represents software, firmware, hardware, or a combinationthereof that, through emulation, simulation or any other process, allowsa processor or other electronic device that does not have an x86instruction set processor or core to execute the x86 binary code 2606.

What is claimed is:
 1. A processor comprising: decode circuitry todecode a load instruction, the load instruction to operate on a pointer,the pointer comprising an address to a block of data in memory and afirst value; and circuitry coupled with the decode circuitry, thecircuitry, based on decode of the load instruction by the decodecircuitry, to: determine whether the first value matches a second valuecorresponding to the block of data; and load the block of data from thememory when the first value matches the second value.
 2. The processorof claim 1, further comprising a configuration register to store data toindicate a number of bits of the first value.
 3. The processor of claim1, further comprising a configuration register to store data to indicatea number of bits of the first value and to store data to indicate aposition of the first value.
 4. The processor of claim 1, furthercomprising a configuration register to have a field to indicate whichbits of the pointer are to include the first value.
 5. The processor ofclaim 1, further comprising a configuration register to store data tocontrol whether the circuitry is to determine whether the first valuematches the second value.
 6. The processor of claim 1, furthercomprising a first set of one or more configuration registers to storedata to control whether the circuitry is to determine whether the firstvalue matches the second value and to store data to indicate a number ofbits of the first value.
 7. The processor of claim 6, further comprisinga second set of one or more configuration registers to store data toindicate a number of bits of a third value to be included in a secondpointer along with a second address.
 8. The processor of claim 1,wherein the first value does not include a most significant bit of thepointer.
 9. The processor of claim 8, wherein the most significant bitof the pointer is to have a value of one for an operating system. 10.The processor of claim 1, wherein the pointer is to have a plurality ofmost significant canonical bits that are all to have a same value. 11.The processor of claim 1, wherein the first value comprises a mostsignificant bit of the pointer.
 12. The processor of claim 1, whereinthe processor is a reduced instruction set computing (RISC) processor,and wherein the first value comprises five bits.
 13. The processor ofclaim 12, wherein the first value comprises ten bits.
 14. The processorof claim 1, wherein the block of data is a 128-bit block of data. 15.The processor of claim 1, wherein the processor is to indicate if thefirst value does not match the second value.
 16. A computer systemcomprising: a dynamic random access memory (DRAM); a processor coupledwith the DRAM, the processor comprising: decode circuitry to decode aload instruction, the load instruction to operate on a pointer, thepointer comprising an address to a block of data in memory and a firstvalue; and circuitry coupled with the decode circuitry, the circuitry,based on decode of the load instruction by the decode circuitry, to:determine whether the first value matches a second value correspondingto the block of data; and load the block of data from the memory whenthe first value matches the second value.
 17. The computer system ofclaim 16, wherein the computer system further comprises a mass storagedevice coupled with the processor, and wherein the processor furthercomprises a configuration register to have a field to indicate whichbits of the pointer are to include the first value.
 18. The computersystem of claim 16, wherein the computer system further comprises acommunication device coupled with the processor, and wherein theprocessor further comprises: a first set of one or more configurationregisters to store data to control whether the circuitry is to determinewhether the first value matches the second value and to store data toindicate a number of bits of the first value; and a second set of one ormore configuration registers to store data to indicate a number of bitsof a third value to be included in a second pointer along with a secondaddress.
 19. The computer system of claim 16, wherein the computersystem further comprises a communication device coupled with theprocessor, wherein the first value comprises five bits, and wherein thepointer is to have a plurality of most significant canonical bits thatare all to have a same value.
 20. A method comprising: decoding a loadinstruction, the load instruction operating on a pointer, the pointercomprising an address to a block of data in memory and a first value;determining whether the first value matches a second value correspondingto the block of data; and loading the block of data from the memory whenthe first value matches the second value.